DMV Display Project
project Overview
In this project we had to design a circuit that counted from 0-80 and would stop at 80. Then when a switch is toggled, the display would reset to 0, and then restart counting.
Multisim Circuit
PLD Circuit
There are some slight differences between PLD mode and design mode. In PLD mode, the inputs and outputs use specific "PIN" connectors so the circuit can be transferred to the CMod S6, and from there to the my Digital Protoboard. This is different compared to the switches and probes used in design mode. To upload the circuit made in PLD mode to the CMod S6, you have to connect the CMod S6 with a USB to the computer. Then you go to the "Transfer" tab in PLD and then click "Export to PLD". This will start the transfer process.
Bill of materials
Conclusions
SSI, or Small-Scale Integration, use logic gates and contain less than 10 gates per IC. MSI, or Medium-Scale Integration uses Flip Flops, Adders/Counters, and Multiplexers & De-multiplexers, and have between 10 and 100 gates per IC. The limits of the MSI circuit are that it can only count up and it can only start from 0. The "ripple effect" is a propagation delay created from the use of asynchronous counters. In this circuit, when the clock runs, the signal travels to the 74LS93, which counts from 0-9 in the ones place.. When the counter detects a 10, the NAND gate resets the load to 0, and the 74LS93 continues counting. The output from the NAND gate in the ones place is the clock for the tens place D flip flops. So when the ones place resets, the tens place increases by one. Once the tens place outputs an 8, an AND gate attached to the input of the 74LS93 causes the entire count to pause until a switch is toggled.